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NEW QUESTION: 1
Which of the following statements about the Decision (HDEFC) decoding and soft decision FEC (SDFEC) decoding is FALSE?
A. HDFEC discards bits earlier in the decoding process than SDEFC.
B. HDFEC provides a higher coding gain than SDEFC
C. HDFEC uses fewer thresholds than SDEFC.
D. HDFEC injects less latency into the decoding process than SDFEC.
Answer: D

NEW QUESTION: 2
Service Release planning happens at the_____level?
A. Enterprise
B. Service
C. Project
D. Operational
Answer: B
Explanation:
The Service Analysis phase is aimed at defining the requirements gathering process, serviceidentification and discovery procedures, as well as determines the SOA release planningstrategy.

NEW QUESTION: 3
Which of the following is a set of data processing elements that increases the performance in a computer by overlapping the steps of different instructions?
A. complex-instruction-set-computer (CISC)
B. pipelining
C. multitasking
D. reduced-instruction-set-computer (RISC)
Answer: B
Explanation:
Pipelining is a natural concept in everyday life, e.g. on an assembly line. Consider the assembly of a car: assume that certain steps in the assembly line are to install the engine,
install the hood, and install the wheels (in that order, with arbitrary interstitial steps). A car on the
assembly line can have only one of the three steps done at once. After the car has its engine
installed, it moves on to having its hood installed, leaving the engine installation facilities available
for the next car. The first car then moves on to wheel installation, the second car to hood
installation, and a third car begins to have its engine installed. If engine installation takes 20
minutes, hood installation takes 5 minutes, and wheel installation takes 10 minutes, then finishing
all three cars when only one car can be assembled at once would take 105 minutes. On the other
hand, using the assembly line, the total time to complete all three is 75 minutes. At this point,
additional cars will come off the assembly line at 20 minute increments.
In computing, a pipeline is a set of data processing elements connected in series, so that the
output of one element is the input of the next one. The elements of a pipeline are often executed in
parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted
between elements. Pipelining is used in processors to allow overlapping execution of multiple
instructions within the same circuitry. The circuitry is usually divided into stages, including
instruction decoding, arithmetic, and register fetching stages, wherein each stage processes one
instruction at a time.
The following were not correct answers:
CISC: is a CPU design where single instructions execute several low-level operations (such as a
load from memory, an arithmetic operation, and a memory store) within a single instruction.
RISC: is a CPU design based on simplified instructions that can provide higher performance as
the simplicity enables much faster execution of each instruction.
Multitasking: is a method where multiple tasks share common processing resources, such as a
CPU, through a method of fast scheduling that gives the appearance of parallelism, but in reality
only one task is being performed at any one time.
Reference:
KRUTZ, Ronald L. & VINES, Russel D., The CISSP Prep Guide: Mastering the Ten Domains of
Computer Security, pages 188-189.
Also see
http://en.wikipedia.org/wiki/Pipeline_(computing)